0x40012000: Analog-to-digital converter
78/78 fields covered. Toggle Registers.
control register 2
Offset: 0x8, reset: 0x00000000, access: read-write
12/12 fields covered.
Bits 16-19: External event select for injected group.
Allowed values:
0: TIM1TRGO: Timer 1 TRGO event
1: TIM1CC4: Timer 1 CC4 event
2: TIM2TRGO: Timer 2 TRGO event
3: TIM2CC1: Timer 2 CC1 event
4: TIM3CC4: Timer 3 CC4 event
5: TIM4TRGO: Timer 4 TRGO event
7: TIM8CC4: Timer 8 CC4 event
8: TIM1TRGO2: Timer 1 TRGO(2) event
9: TIM8TRGO: Timer 8 TRGO event
10: TIM8TRGO2: Timer 8 TRGO(2) event
11: TIM3CC3: Timer 3 CC3 event
12: TIM5TRGO: Timer 5 TRGO event
13: TIM3CC1: Timer 3 CC1 event
14: TIM6TRGO: Timer 6 TRGO event
injected channel data offset register x
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JOFFSET
rw |
|||||||||||||||
watchdog higher threshold register
Offset: 0x24, reset: 0x00000FFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HT
rw |
|||||||||||||||
watchdog lower threshold register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT
rw |
|||||||||||||||
injected data register x
Offset: 0x3C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA
r |
|||||||||||||||
regular data register
Offset: 0x4C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATA
r |
|||||||||||||||
0x40012100: Analog-to-digital converter
78/78 fields covered. Toggle Registers.
control register 2
Offset: 0x8, reset: 0x00000000, access: read-write
12/12 fields covered.
Bits 16-19: External event select for injected group.
Allowed values:
0: TIM1TRGO: Timer 1 TRGO event
1: TIM1CC4: Timer 1 CC4 event
2: TIM2TRGO: Timer 2 TRGO event
3: TIM2CC1: Timer 2 CC1 event
4: TIM3CC4: Timer 3 CC4 event
5: TIM4TRGO: Timer 4 TRGO event
7: TIM8CC4: Timer 8 CC4 event
8: TIM1TRGO2: Timer 1 TRGO(2) event
9: TIM8TRGO: Timer 8 TRGO event
10: TIM8TRGO2: Timer 8 TRGO(2) event
11: TIM3CC3: Timer 3 CC3 event
12: TIM5TRGO: Timer 5 TRGO event
13: TIM3CC1: Timer 3 CC1 event
14: TIM6TRGO: Timer 6 TRGO event
injected channel data offset register x
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JOFFSET
rw |
|||||||||||||||
watchdog higher threshold register
Offset: 0x24, reset: 0x00000FFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HT
rw |
|||||||||||||||
watchdog lower threshold register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT
rw |
|||||||||||||||
injected data register x
Offset: 0x3C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA
r |
|||||||||||||||
regular data register
Offset: 0x4C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATA
r |
|||||||||||||||
0x40012200: Analog-to-digital converter
78/78 fields covered. Toggle Registers.
control register 2
Offset: 0x8, reset: 0x00000000, access: read-write
12/12 fields covered.
Bits 16-19: External event select for injected group.
Allowed values:
0: TIM1TRGO: Timer 1 TRGO event
1: TIM1CC4: Timer 1 CC4 event
2: TIM2TRGO: Timer 2 TRGO event
3: TIM2CC1: Timer 2 CC1 event
4: TIM3CC4: Timer 3 CC4 event
5: TIM4TRGO: Timer 4 TRGO event
7: TIM8CC4: Timer 8 CC4 event
8: TIM1TRGO2: Timer 1 TRGO(2) event
9: TIM8TRGO: Timer 8 TRGO event
10: TIM8TRGO2: Timer 8 TRGO(2) event
11: TIM3CC3: Timer 3 CC3 event
12: TIM5TRGO: Timer 5 TRGO event
13: TIM3CC1: Timer 3 CC1 event
14: TIM6TRGO: Timer 6 TRGO event
injected channel data offset register x
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JOFFSET
rw |
|||||||||||||||
watchdog higher threshold register
Offset: 0x24, reset: 0x00000FFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HT
rw |
|||||||||||||||
watchdog lower threshold register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT
rw |
|||||||||||||||
injected data register x
Offset: 0x3C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA
r |
|||||||||||||||
regular data register
Offset: 0x4C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATA
r |
|||||||||||||||
0x40012300: Common ADC registers
27/27 fields covered. Toggle Registers.
ADC common control register
Offset: 0x4, reset: 0x00000000, access: read-write
7/7 fields covered.
Bits 0-4: Multi ADC mode selection.
Allowed values:
0: Independent: All the ADCs independent: independent mode
1: DualRJ: Dual ADC1 and ADC2, combined regular and injected simultaneous mode
2: DualRA: Dual ADC1 and ADC2, combined regular and alternate trigger mode
5: DualJ: Dual ADC1 and ADC2, injected simultaneous mode only
6: DualR: Dual ADC1 and ADC2, regular simultaneous mode only
7: DualI: Dual ADC1 and ADC2, interleaved mode only
9: DualA: Dual ADC1 and ADC2, alternate trigger mode only
17: TripleRJ: Triple ADC, regular and injected simultaneous mode
18: TripleRA: Triple ADC, regular and alternate trigger mode
21: TripleJ: Triple ADC, injected simultaneous mode only
22: TripleR: Triple ADC, regular simultaneous mode only
23: TripleI: Triple ADC, interleaved mode only
24: TripleA: Triple ADC, alternate trigger mode only
Bits 14-15: Direct memory access mode for multi ADC mode.
Allowed values:
0: Disabled: DMA mode disabled
1: Mode1: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
2: Mode2: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
3: Mode3: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
ADC common regular data register for dual and triple modes
Offset: 0x8, reset: 0x00000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DATA2
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATA1
r |
|||||||||||||||
0x40006400: Controller area network
57/218 fields covered. Toggle Registers.
receive FIFO %s register
Offset: 0xC, reset: 0x00000000, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RFOM
rw |
FOVR
rw |
FULL
rw |
FMP
r |
||||||||||||
filter master register
Offset: 0x200, reset: 0x2A1C0E01, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CAN2SB
rw |
FINIT
rw |
||||||||||||||
filter mode register
Offset: 0x204, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FBM27
rw |
FBM26
rw |
FBM25
rw |
FBM24
rw |
FBM23
rw |
FBM22
rw |
FBM21
rw |
FBM20
rw |
FBM19
rw |
FBM18
rw |
FBM17
rw |
FBM16
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FBM15
rw |
FBM14
rw |
FBM13
rw |
FBM12
rw |
FBM11
rw |
FBM10
rw |
FBM9
rw |
FBM8
rw |
FBM7
rw |
FBM6
rw |
FBM5
rw |
FBM4
rw |
FBM3
rw |
FBM2
rw |
FBM1
rw |
FBM0
rw |
filter scale register
Offset: 0x20C, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FSC27
rw |
FSC26
rw |
FSC25
rw |
FSC24
rw |
FSC23
rw |
FSC22
rw |
FSC21
rw |
FSC20
rw |
FSC19
rw |
FSC18
rw |
FSC17
rw |
FSC16
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FSC15
rw |
FSC14
rw |
FSC13
rw |
FSC12
rw |
FSC11
rw |
FSC10
rw |
FSC9
rw |
FSC8
rw |
FSC7
rw |
FSC6
rw |
FSC5
rw |
FSC4
rw |
FSC3
rw |
FSC2
rw |
FSC1
rw |
FSC0
rw |
filter FIFO assignment register
Offset: 0x214, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FFA27
rw |
FFA26
rw |
FFA25
rw |
FFA24
rw |
FFA23
rw |
FFA22
rw |
FFA21
rw |
FFA20
rw |
FFA19
rw |
FFA18
rw |
FFA17
rw |
FFA16
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FFA15
rw |
FFA14
rw |
FFA13
rw |
FFA12
rw |
FFA11
rw |
FFA10
rw |
FFA9
rw |
FFA8
rw |
FFA7
rw |
FFA6
rw |
FFA5
rw |
FFA4
rw |
FFA3
rw |
FFA2
rw |
FFA1
rw |
FFA0
rw |
filter activation register
Offset: 0x21C, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FACT27
rw |
FACT26
rw |
FACT25
rw |
FACT24
rw |
FACT23
rw |
FACT22
rw |
FACT21
rw |
FACT20
rw |
FACT19
rw |
FACT18
rw |
FACT17
rw |
FACT16
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FACT15
rw |
FACT14
rw |
FACT13
rw |
FACT12
rw |
FACT11
rw |
FACT10
rw |
FACT9
rw |
FACT8
rw |
FACT7
rw |
FACT6
rw |
FACT5
rw |
FACT4
rw |
FACT3
rw |
FACT2
rw |
FACT1
rw |
FACT0
rw |
0x40006800: Controller area network
57/218 fields covered. Toggle Registers.
receive FIFO %s register
Offset: 0xC, reset: 0x00000000, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RFOM
rw |
FOVR
rw |
FULL
rw |
FMP
r |
||||||||||||
filter master register
Offset: 0x200, reset: 0x2A1C0E01, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CAN2SB
rw |
FINIT
rw |
||||||||||||||
filter mode register
Offset: 0x204, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FBM27
rw |
FBM26
rw |
FBM25
rw |
FBM24
rw |
FBM23
rw |
FBM22
rw |
FBM21
rw |
FBM20
rw |
FBM19
rw |
FBM18
rw |
FBM17
rw |
FBM16
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FBM15
rw |
FBM14
rw |
FBM13
rw |
FBM12
rw |
FBM11
rw |
FBM10
rw |
FBM9
rw |
FBM8
rw |
FBM7
rw |
FBM6
rw |
FBM5
rw |
FBM4
rw |
FBM3
rw |
FBM2
rw |
FBM1
rw |
FBM0
rw |
filter scale register
Offset: 0x20C, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FSC27
rw |
FSC26
rw |
FSC25
rw |
FSC24
rw |
FSC23
rw |
FSC22
rw |
FSC21
rw |
FSC20
rw |
FSC19
rw |
FSC18
rw |
FSC17
rw |
FSC16
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FSC15
rw |
FSC14
rw |
FSC13
rw |
FSC12
rw |
FSC11
rw |
FSC10
rw |
FSC9
rw |
FSC8
rw |
FSC7
rw |
FSC6
rw |
FSC5
rw |
FSC4
rw |
FSC3
rw |
FSC2
rw |
FSC1
rw |
FSC0
rw |
filter FIFO assignment register
Offset: 0x214, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FFA27
rw |
FFA26
rw |
FFA25
rw |
FFA24
rw |
FFA23
rw |
FFA22
rw |
FFA21
rw |
FFA20
rw |
FFA19
rw |
FFA18
rw |
FFA17
rw |
FFA16
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FFA15
rw |
FFA14
rw |
FFA13
rw |
FFA12
rw |
FFA11
rw |
FFA10
rw |
FFA9
rw |
FFA8
rw |
FFA7
rw |
FFA6
rw |
FFA5
rw |
FFA4
rw |
FFA3
rw |
FFA2
rw |
FFA1
rw |
FFA0
rw |
filter activation register
Offset: 0x21C, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FACT27
rw |
FACT26
rw |
FACT25
rw |
FACT24
rw |
FACT23
rw |
FACT22
rw |
FACT21
rw |
FACT20
rw |
FACT19
rw |
FACT18
rw |
FACT17
rw |
FACT16
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FACT15
rw |
FACT14
rw |
FACT13
rw |
FACT12
rw |
FACT11
rw |
FACT10
rw |
FACT9
rw |
FACT8
rw |
FACT7
rw |
FACT6
rw |
FACT5
rw |
FACT4
rw |
FACT3
rw |
FACT2
rw |
FACT1
rw |
FACT0
rw |
0x40023000: Cryptographic processor
3/3 fields covered. Toggle Registers.
Data register
Offset: 0x0, reset: 0xFFFFFFFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Independent Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IDR
rw |
|||||||||||||||
Control register
Offset: 0x8, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RESET
w |
|||||||||||||||
0x50060000: Cryptographic processor
10/29 fields covered. Toggle Registers.
data input register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DATAIN
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATAIN
rw |
|||||||||||||||
data output register
Offset: 0xC, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DATAOUT
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATAOUT
r |
|||||||||||||||
DMA control register
Offset: 0x10, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DOEN
rw |
DIEN
rw |
||||||||||||||
interrupt mask set/clear register
Offset: 0x14, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OUTIM
rw |
INIM
rw |
||||||||||||||
raw interrupt status register
Offset: 0x18, reset: 0x00000001, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OUTRIS
r |
INRIS
r |
||||||||||||||
masked interrupt status register
Offset: 0x1C, reset: 0x00000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OUTMIS
r |
INMIS
r |
||||||||||||||
context swap register
Offset: 0x50, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CSGCMCCM0R
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CSGCMCCM0R
rw |
|||||||||||||||
context swap register
Offset: 0x70, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CSGCMR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CSGCMR
rw |
|||||||||||||||
0x40007400: Digital-to-analog converter
34/34 fields covered. Toggle Registers.
control register
Offset: 0x0, reset: 0x00000000, access: read-write
16/16 fields covered.
Bits 19-21: DAC channel2 trigger selection.
Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM8_TRGO: Timer 8 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM5_TRGO: Timer 5 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger
software trigger register
Offset: 0x4, reset: 0x00000000, access: write-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWTRIG2
w |
SWTRIG1
w |
||||||||||||||
channel1 12-bit right-aligned data holding register
Offset: 0x8, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
channel1 12-bit left aligned data holding register
Offset: 0xC, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
channel1 8-bit right aligned data holding register
Offset: 0x10, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
channel2 12-bit right aligned data holding register
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
channel2 12-bit left aligned data holding register
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
channel2 8-bit right-aligned data holding register
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
Dual DAC 12-bit right-aligned data holding register
Offset: 0x20, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DUAL DAC 12-bit left aligned data holding register
Offset: 0x24, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DUAL DAC 8-bit right aligned data holding register
Offset: 0x28, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
DACC1DHR
rw |
||||||||||||||
channel1 data output register
Offset: 0x2C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DOR
r |
|||||||||||||||
channel2 data output register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DOR
r |
|||||||||||||||
status register
Offset: 0x34, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAUDR2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAUDR1
rw |
|||||||||||||||
0xE0042000: Debug support
2/33 fields covered. Toggle Registers.
IDCODE
Offset: 0x0, reset: 0x10006411, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REV_ID
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEV_ID
r |
|||||||||||||||
Control Register
Offset: 0x4, reset: 0x00000000, access: read-write
0/10 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DBG_TIM7_STOP
rw |
DBG_TIM6_STOP
rw |
DBG_TIM5_STOP
rw |
DBG_TIM8_STOP
rw |
DBG_I2C2_SMBUS_TIMEOUT
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRACE_MODE
rw |
TRACE_IOEN
rw |
DBG_STANDBY
rw |
DBG_STOP
rw |
DBG_SLEEP
rw |
|||||||||||
Debug MCU APB1 Freeze registe
Offset: 0x8, reset: 0x00000000, access: read-write
0/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DBG_CAN2_STOP
rw |
DBG_CAN1_STOP
rw |
DBG_J2C3SMBUS_TIMEOUT
rw |
DBG_J2C2_SMBUS_TIMEOUT
rw |
DBG_J2C1_SMBUS_TIMEOUT
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBG_IWDG_STOP
rw |
DBG_WWDG_STOP
rw |
DBG_TIM14_STOP
rw |
DBG_TIM13_STOP
rw |
DBG_TIM12_STOP
rw |
DBG_TIM7_STOP
rw |
DBG_TIM6_STOP
rw |
DBG_TIM5_STOP
rw |
DBG_TIM4_STOP
rw |
DBG_TIM3_STOP
rw |
DBG_TIM2_STOP
rw |
|||||
Debug MCU APB2 Freeze registe
Offset: 0xC, reset: 0x00000000, access: read-write
0/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DBG_TIM11_STOP
rw |
DBG_TIM10_STOP
rw |
DBG_TIM9_STOP
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBG_TIM8_STOP
rw |
DBG_TIM1_STOP
rw |
||||||||||||||
0x50050000: Digital camera interface
17/50 fields covered. Toggle Registers.
status register
Offset: 0x4, reset: 0x0000, access: read-only
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FNE
r |
VSYNC
r |
HSYNC
r |
|||||||||||||
embedded synchronization code register
Offset: 0x18, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FEC
rw |
LEC
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LSC
rw |
FSC
rw |
||||||||||||||
embedded synchronization unmask register
Offset: 0x1C, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FEU
rw |
LEU
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LSU
rw |
FSU
rw |
||||||||||||||
crop window start
Offset: 0x20, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
VST
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HOFFCNT
rw |
|||||||||||||||
crop window size
Offset: 0x24, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
VLINE
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CAPCNT
rw |
|||||||||||||||
data register
Offset: 0x28, reset: 0x0000, access: read-only
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Byte3
r |
Byte2
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Byte1
r |
Byte0
r |
||||||||||||||
0x40026000: DMA controller
104/107 fields covered. Toggle Registers.
stream x memory 1 address register
Offset: 0x10, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x14, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
0x40026400: DMA controller
104/107 fields covered. Toggle Registers.
stream x memory 1 address register
Offset: 0x10, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x14, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
0x40029000: Ethernet: DMA controller operation
10/73 fields covered. Toggle Registers.
Ethernet DMA transmit poll demand register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TPD
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TPD
rw |
|||||||||||||||
EHERNET DMA receive poll demand register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RPD
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RPD
rw |
|||||||||||||||
Ethernet DMA receive descriptor list address register
Offset: 0xC, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SRL
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SRL
rw |
|||||||||||||||
Ethernet DMA transmit descriptor list address register
Offset: 0x10, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
STL
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STL
rw |
|||||||||||||||
Ethernet DMA missed frame and buffer overflow counter register
Offset: 0x20, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OFOC
rw |
MFA
rw |
OMFC
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MFC
rw |
|||||||||||||||
Ethernet DMA receive status watchdog timer register
Offset: 0x24, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RSWTC
rw |
|||||||||||||||
Ethernet DMA current host transmit descriptor register
Offset: 0x48, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HTDAP
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HTDAP
r |
|||||||||||||||
Ethernet DMA current host receive descriptor register
Offset: 0x4C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HRDAP
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HRDAP
r |
|||||||||||||||
Ethernet DMA current host transmit buffer address register
Offset: 0x50, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HTBAP
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HTBAP
r |
|||||||||||||||
Ethernet DMA current host receive buffer address register
Offset: 0x54, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HRBAP
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HRBAP
r |
|||||||||||||||
0x40028000: Ethernet: media access control (MAC)
11/82 fields covered. Toggle Registers.
Ethernet MAC hash table high register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HTH
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HTH
rw |
|||||||||||||||
Ethernet MAC hash table low register
Offset: 0xC, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HTL
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HTL
rw |
|||||||||||||||
Ethernet MAC MII data register
Offset: 0x14, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TD
rw |
|||||||||||||||
Ethernet MAC VLAN tag register
Offset: 0x1C, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
VLANTC
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VLANTI
rw |
|||||||||||||||
Ethernet MAC interrupt mask register
Offset: 0x3C, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSTIM
rw |
PMTIM
rw |
||||||||||||||
Ethernet MAC address 0 high register
Offset: 0x40, reset: 0x0010FFFF, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MO
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MACA0H
rw |
|||||||||||||||
Ethernet MAC address 0 low register
Offset: 0x44, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MACA0L
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MACA0L
rw |
|||||||||||||||
Ethernet MAC address 1 high register
Offset: 0x48, reset: 0x0000FFFF, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AE
rw |
SA
rw |
MBC
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MACA1H
rw |
|||||||||||||||
Ethernet MAC address1 low register
Offset: 0x4C, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MACA1LR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MACA1LR
rw |
|||||||||||||||
Ethernet MAC address 2 high register
Offset: 0x50, reset: 0x0000FFFF, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AE
rw |
SA
rw |
MBC
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MAC2AH
rw |
|||||||||||||||
Ethernet MAC address 2 low register
Offset: 0x54, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MACA2L
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MACA2L
rw |
|||||||||||||||
Ethernet MAC address 3 high register
Offset: 0x58, reset: 0x0000FFFF, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AE
rw |
SA
rw |
MBC
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MACA3H
rw |
|||||||||||||||
Ethernet MAC address 3 low register
Offset: 0x5C, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MBCA3L
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MBCA3L
rw |
|||||||||||||||
0x40028100: Ethernet: MAC management counters
9/24 fields covered. Toggle Registers.
Ethernet MMC receive interrupt register
Offset: 0x4, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RGUFS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RFAES
rw |
RFCES
rw |
||||||||||||||
Ethernet MMC transmit interrupt register
Offset: 0x8, reset: 0x00000000, access: read-only
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TGFS
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TGFMSCS
r |
TGFSCS
r |
||||||||||||||
Ethernet MMC receive interrupt mask register
Offset: 0xC, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RGUFM
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RFAEM
rw |
RFCEM
rw |
||||||||||||||
Ethernet MMC transmit interrupt mask register
Offset: 0x10, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TGFM
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TGFMSCM
rw |
TGFSCM
rw |
||||||||||||||
Ethernet MMC transmitted good frames after a single collision counter
Offset: 0x4C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TGFSCC
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TGFSCC
r |
|||||||||||||||
Ethernet MMC transmitted good frames after more than a single collision
Offset: 0x50, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TGFMSCC
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TGFMSCC
r |
|||||||||||||||
Ethernet MMC transmitted good frames counter register
Offset: 0x68, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TGFC
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TGFC
r |
|||||||||||||||
Ethernet MMC received frames with CRC error counter register
Offset: 0x94, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RFCFC
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RFCFC
r |
|||||||||||||||
Ethernet MMC received frames with alignment error counter register
Offset: 0x98, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RFAEC
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RFAEC
r |
|||||||||||||||
MMC received good unicast frames counter register
Offset: 0xC4, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RGUFC
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RGUFC
r |
|||||||||||||||
0x40028700: Ethernet: Precision time protocol
7/30 fields covered. Toggle Registers.
Ethernet PTP subsecond increment register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STSSI
rw |
|||||||||||||||
Ethernet PTP time stamp high register
Offset: 0x8, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
STS
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STS
r |
|||||||||||||||
Ethernet PTP time stamp low register
Offset: 0xC, reset: 0x00000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
STPNS
r |
STSS
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STSS
r |
|||||||||||||||
Ethernet PTP time stamp high update register
Offset: 0x10, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TSUS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSUS
rw |
|||||||||||||||
Ethernet PTP time stamp low update register
Offset: 0x14, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TSUPNS
rw |
TSUSS
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSUSS
rw |
|||||||||||||||
Ethernet PTP time stamp addend register
Offset: 0x18, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TSA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSA
rw |
|||||||||||||||
Ethernet PTP target time high register
Offset: 0x1C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TTSH
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TTSH
rw |
|||||||||||||||
Ethernet PTP target time low register
Offset: 0x20, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TTSL
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TTSL
rw |
|||||||||||||||
Ethernet PTP time stamp status register
Offset: 0x28, reset: 0x00000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSTTR
r |
TSSO
r |
||||||||||||||
Ethernet PTP PPS control register
Offset: 0x2C, reset: 0x00000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSTTR
r |
TSSO
r |
||||||||||||||
0x40013C00: External interrupt/event controller
138/138 fields covered. Toggle Registers.
Software interrupt event register (EXTI_SWIER)
Offset: 0x10, reset: 0x00000000, access: read-write
23/23 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SWIER22
rw |
SWIER21
rw |
SWIER20
rw |
SWIER19
rw |
SWIER18
rw |
SWIER17
rw |
SWIER16
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWIER15
rw |
SWIER14
rw |
SWIER13
rw |
SWIER12
rw |
SWIER11
rw |
SWIER10
rw |
SWIER9
rw |
SWIER8
rw |
SWIER7
rw |
SWIER6
rw |
SWIER5
rw |
SWIER4
rw |
SWIER3
rw |
SWIER2
rw |
SWIER1
rw |
SWIER0
rw |
0x40023C00: FLASH
18/32 fields covered. Toggle Registers.
Flash key register
Offset: 0x4, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
KEY
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
KEY
w |
|||||||||||||||
Flash option key register
Offset: 0x8, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OPTKEY
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OPTKEY
w |
|||||||||||||||
Flash option control register
Offset: 0x14, reset: 0x00000014, access: read-write
0/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
nWRP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDP
rw |
nRST_STDBY
rw |
nRST_STOP
rw |
WDG_SW
rw |
BOR_LEV
rw |
OPTSTRT
rw |
OPTLOCK
rw |
|||||||||
0xE000EF34: Floting point unit
0/24 fields covered. Toggle Registers.
Floating-point context address register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADDRESS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADDRESS
rw |
|||||||||||||||
0xE000ED88: Floating point unit CPACR
0/1 fields covered. Toggle Registers.
Coprocessor access control register
Offset: 0x0, reset: 0x0000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0xA0000000: Flexible static memory controller
81/89 fields covered. Toggle Registers.
Common memory space timing register 2
Offset: 0x68, reset: 0xFCFCFCFC, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEMHIZ
rw |
MEMHOLD
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MEMWAIT
rw |
MEMSET
rw |
||||||||||||||
Attribute memory space timing register 2
Offset: 0x6C, reset: 0xFCFCFCFC, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ATTHIZ
rw |
ATTHOLD
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ATTWAIT
rw |
ATTSET
rw |
||||||||||||||
ECC result register 2
Offset: 0x74, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ECC
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ECC
r |
|||||||||||||||
Common memory space timing register 3
Offset: 0x88, reset: 0xFCFCFCFC, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEMHIZ
rw |
MEMHOLD
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MEMWAIT
rw |
MEMSET
rw |
||||||||||||||
Attribute memory space timing register 3
Offset: 0x8C, reset: 0xFCFCFCFC, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ATTHIZ
rw |
ATTHOLD
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ATTWAIT
rw |
ATTSET
rw |
||||||||||||||
ECC result register 3
Offset: 0x94, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ECC
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ECC
r |
|||||||||||||||
Common memory space timing register 4
Offset: 0xA8, reset: 0xFCFCFCFC, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEMHIZ
rw |
MEMHOLD
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MEMWAIT
rw |
MEMSET
rw |
||||||||||||||
Attribute memory space timing register 4
Offset: 0xAC, reset: 0xFCFCFCFC, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ATTHIZ
rw |
ATTHOLD
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ATTWAIT
rw |
ATTSET
rw |
||||||||||||||
I/O space timing register 4
Offset: 0xB0, reset: 0xFCFCFCFC, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IOHIZx
rw |
IOHOLDx
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IOWAITx
rw |
IOSETx
rw |
||||||||||||||
0x40020000: General-purpose I/Os
161/161 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40020400: General-purpose I/Os
161/161 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40020800: General-purpose I/Os
161/161 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0X40020C00: General-purpose I/Os
161/161 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40021000: General-purpose I/Os
161/161 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40021400: General-purpose I/Os
161/161 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40021800: General-purpose I/Os
161/161 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40021C00: General-purpose I/Os
161/161 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40022000: General-purpose I/Os
161/161 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40022400: General-purpose I/Os
161/161 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40022800: General-purpose I/Os
161/161 fields covered. Toggle Registers.
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x50060400: Hash processor
6/22 fields covered. Toggle Registers.
data input register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DATAIN
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATAIN
rw |
|||||||||||||||
start register
Offset: 0x8, reset: 0x00000000, access: Unspecified
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DCAL
w |
NBLW
rw |
||||||||||||||
digest registers
Offset: 0xC, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
H
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
H
r |
|||||||||||||||
interrupt enable register
Offset: 0x20, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DCIE
rw |
DINIE
rw |
||||||||||||||
status register
Offset: 0x24, reset: 0x00000001, access: Unspecified
2/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BUSY
r |
DMAS
r |
DCIS
rw |
DINIS
rw |
||||||||||||
context swap registers
Offset: 0xF8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CSR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CSR
rw |
|||||||||||||||
HASH digest register
Offset: 0x310, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
H
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
H
r |
|||||||||||||||
0x40005400: Inter-integrated circuit
51/51 fields covered. Toggle Registers.
Own address register 1
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADDMODE
rw |
ADD
rw |
||||||||||||||
Own address register 2
Offset: 0xC, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADD2
rw |
ENDUAL
rw |
||||||||||||||
Data register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Status register 2
Offset: 0x18, reset: 0x0000, access: read-only
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PEC
r |
DUALF
r |
SMBHOST
r |
SMBDEFAULT
r |
GENCALL
r |
TRA
r |
BUSY
r |
MSL
r |
||||||||
Clock control register
Offset: 0x1C, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
F_S
rw |
DUTY
rw |
CCR
rw |
|||||||||||||
TRISE register
Offset: 0x20, reset: 0x0002, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRISE
rw |
|||||||||||||||
0x40005800: Inter-integrated circuit
51/51 fields covered. Toggle Registers.
Own address register 1
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADDMODE
rw |
ADD
rw |
||||||||||||||
Own address register 2
Offset: 0xC, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADD2
rw |
ENDUAL
rw |
||||||||||||||
Data register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Status register 2
Offset: 0x18, reset: 0x0000, access: read-only
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PEC
r |
DUALF
r |
SMBHOST
r |
SMBDEFAULT
r |
GENCALL
r |
TRA
r |
BUSY
r |
MSL
r |
||||||||
Clock control register
Offset: 0x1C, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
F_S
rw |
DUTY
rw |
CCR
rw |
|||||||||||||
TRISE register
Offset: 0x20, reset: 0x0002, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRISE
rw |
|||||||||||||||
0x40005C00: Inter-integrated circuit
51/51 fields covered. Toggle Registers.
Own address register 1
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADDMODE
rw |
ADD
rw |
||||||||||||||
Own address register 2
Offset: 0xC, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADD2
rw |
ENDUAL
rw |
||||||||||||||
Data register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Status register 2
Offset: 0x18, reset: 0x0000, access: read-only
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PEC
r |
DUALF
r |
SMBHOST
r |
SMBDEFAULT
r |
GENCALL
r |
TRA
r |
BUSY
r |
MSL
r |
||||||||
Clock control register
Offset: 0x1C, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
F_S
rw |
DUTY
rw |
CCR
rw |
|||||||||||||
TRISE register
Offset: 0x20, reset: 0x0002, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRISE
rw |
|||||||||||||||
0x40003400: Serial peripheral interface
45/45 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40004000: Serial peripheral interface
45/45 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40003000: Independent watchdog
5/5 fields covered. Toggle Registers.
Key register
Offset: 0x0, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
KEY
w |
|||||||||||||||
Prescaler register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PR
rw |
|||||||||||||||
Reload register
Offset: 0x8, reset: 0x00000FFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RL
rw |
|||||||||||||||
Status register
Offset: 0xC, reset: 0x00000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RVU
r |
PVU
r |
||||||||||||||
0x40016800: LCD-TFT Controller
67/67 fields covered. Toggle Registers.
Layerx Control Register
Offset: 0x0, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLUTEN
rw |
COLKEN
rw |
LEN
rw |
|||||||||||||
Layerx Window Horizontal Position Configuration Register
Offset: 0x4, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WHSPPOS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WHSTPOS
rw |
|||||||||||||||
Synchronization Size Configuration Register
Offset: 0x8, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HSW
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VSH
rw |
|||||||||||||||
Back Porch Configuration Register
Offset: 0xC, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AHBP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AVBP
rw |
|||||||||||||||
Active Width Configuration Register
Offset: 0x10, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AAW
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AAH
rw |
|||||||||||||||
Total Width Configuration Register
Offset: 0x14, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TOTALW
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TOTALH
rw |
|||||||||||||||
Layerx Blending Factors Configuration Register
Offset: 0x1C, reset: 0x00000607, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BF1
rw |
BF2
rw |
||||||||||||||
Shadow Reload Configuration Register
Offset: 0x24, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VBR
rw |
IMR
rw |
||||||||||||||
Bit 0: Immediate Reload.
Allowed values:
1: Reload: The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload
0: NoEffect: This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)
Bit 1: Vertical Blanking Reload.
Allowed values:
1: Reload: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area).
0: NoEffect: This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)
Layerx Color Frame Buffer Address Register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CFBADD
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CFBADD
rw |
|||||||||||||||
Background Color Configuration Register
Offset: 0x2C, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BCRED
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BCGREEN
rw |
BCBLUE
rw |
||||||||||||||
Layerx ColorFrame Buffer Line Number Register
Offset: 0x30, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CFBLNBR
rw |
|||||||||||||||
Interrupt Enable Register
Offset: 0x34, reset: 0x00000000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RRIE
rw |
TERRIE
rw |
FUIE
rw |
LIE
rw |
||||||||||||
Interrupt Status Register
Offset: 0x38, reset: 0x00000000, access: read-only
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RRIF
r |
TERRIF
r |
FUIF
r |
LIF
r |
||||||||||||
Interrupt Clear Register
Offset: 0x3C, reset: 0x00000000, access: write-only
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRRIF
w |
CTERRIF
w |
CFUIF
w |
CLIF
w |
||||||||||||
Line Interrupt Position Configuration Register
Offset: 0x40, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LIPOS
rw |
|||||||||||||||
Current Position Status Register
Offset: 0x44, reset: 0x00000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CXPOS
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CYPOS
r |
|||||||||||||||
Current Display Status Register
Offset: 0x48, reset: 0x0000000F, access: read-only
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HSYNCS
r |
VSYNCS
r |
HDES
r |
VDES
r |
||||||||||||
0xE000ED90: Memory protection unit
6/19 fields covered. Toggle Registers.
MPU type register
Offset: 0x0, reset: 0X00000800, access: read-only
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IREGION
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DREGION
r |
SEPARATE
r |
||||||||||||||
MPU control register
Offset: 0x4, reset: 0X00000000, access: read-only
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRIVDEFENA
r |
HFNMIENA
r |
ENABLE
r |
|||||||||||||
MPU region number register
Offset: 0x8, reset: 0X00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REGION
rw |
|||||||||||||||
MPU region base address register
Offset: 0xC, reset: 0X00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADDR
rw |
VALID
rw |
REGION
rw |
|||||||||||||
0xE000E100: Nested Vectored Interrupt Controller
3/95 fields covered. Toggle Registers.
Interrupt Set-Enable Register
Offset: 0x0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETENA
rw |
|||||||||||||||
Interrupt Set-Enable Register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETENA
rw |
|||||||||||||||
Interrupt Set-Enable Register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETENA
rw |
|||||||||||||||
Interrupt Clear-Enable Register
Offset: 0x80, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRENA
rw |
|||||||||||||||
Interrupt Clear-Enable Register
Offset: 0x84, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRENA
rw |
|||||||||||||||
Interrupt Clear-Enable Register
Offset: 0x88, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRENA
rw |
|||||||||||||||
Interrupt Set-Pending Register
Offset: 0x100, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETPEND
rw |
|||||||||||||||
Interrupt Set-Pending Register
Offset: 0x104, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETPEND
rw |
|||||||||||||||
Interrupt Set-Pending Register
Offset: 0x108, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETPEND
rw |
|||||||||||||||
Interrupt Clear-Pending Register
Offset: 0x180, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRPEND
rw |
|||||||||||||||
Interrupt Clear-Pending Register
Offset: 0x184, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRPEND
rw |
|||||||||||||||
Interrupt Clear-Pending Register
Offset: 0x188, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRPEND
rw |
|||||||||||||||
Interrupt Active Bit Register
Offset: 0x200, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ACTIVE
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ACTIVE
r |
|||||||||||||||
Interrupt Active Bit Register
Offset: 0x204, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ACTIVE
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ACTIVE
r |
|||||||||||||||
Interrupt Active Bit Register
Offset: 0x208, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ACTIVE
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ACTIVE
r |
|||||||||||||||
Interrupt Priority Register
Offset: 0x300, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x304, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x308, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x30C, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x310, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x314, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x318, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x31C, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x320, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x324, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x328, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x32C, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x330, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x334, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x338, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x33C, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x340, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x344, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x348, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x34C, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
0xE000EF00: Nested vectored interrupt controller
0/1 fields covered. Toggle Registers.
Software trigger interrupt register
Offset: 0x0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INTID
rw |
|||||||||||||||
0x50000800: USB on the go full speed
29/152 fields covered. Toggle Registers.
OTG_FS device configuration register (OTG_FS_DCFG)
Offset: 0x0, reset: 0x02200000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PFIVL
rw |
DAD
rw |
NZLSOHSK
rw |
DSPD
rw |
||||||||||||
OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
Offset: 0x14, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OTEPDM
rw |
STUPM
rw |
EPDM
rw |
XFRCM
rw |
||||||||||||
OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
Offset: 0x18, reset: 0x00000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OEPINT
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IEPINT
r |
|||||||||||||||
OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
Offset: 0x1C, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OEPM
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IEPM
rw |
|||||||||||||||
OTG_FS device VBUS discharge time register
Offset: 0x28, reset: 0x000017D7, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VBUSDT
rw |
|||||||||||||||
OTG_FS device VBUS pulsing time register
Offset: 0x2C, reset: 0x000005B8, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DVBUSP
rw |
|||||||||||||||
OTG_FS device IN endpoint FIFO empty interrupt mask register
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INEPTXFEM
rw |
|||||||||||||||
device endpoint-0 transfer size register
Offset: 0x110, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PKTCNT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_FS device IN endpoint transmit FIFO status register
Offset: 0x118, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INEPTFSAV
r |
|||||||||||||||
OTG device endpoint-1 control register
Offset: 0x120, reset: 0x00000000, access: Unspecified
2/13 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EPENA
rw |
EPDIS
rw |
SODDFRM_SD1PID
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
TXFNUM
rw |
STALL
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
USBAEP
rw |
MPSIZ
rw |
||||||||||||||
device endpoint-1 transfer size register
Offset: 0x130, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_FS device IN endpoint transmit FIFO status register
Offset: 0x138, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INEPTFSAV
r |
|||||||||||||||
device endpoint-2 transfer size register
Offset: 0x150, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_FS device IN endpoint transmit FIFO status register
Offset: 0x158, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INEPTFSAV
r |
|||||||||||||||
device endpoint-3 transfer size register
Offset: 0x170, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_FS device IN endpoint transmit FIFO status register
Offset: 0x178, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INEPTFSAV
r |
|||||||||||||||
device OUT endpoint-0 transfer size register
Offset: 0x310, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
STUPCNT
rw |
PKTCNT
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
device endpoint-1 control register
Offset: 0x320, reset: 0x00000000, access: Unspecified
2/13 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EPENA
rw |
EPDIS
rw |
SODDFRM
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
STALL
rw |
SNPM
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
USBAEP
rw |
MPSIZ
rw |
||||||||||||||
device OUT endpoint-1 transfer size register
Offset: 0x330, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RXDPID_STUPCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
device OUT endpoint-2 transfer size register
Offset: 0x350, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RXDPID_STUPCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
device OUT endpoint-3 transfer size register
Offset: 0x370, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RXDPID_STUPCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
0x50000000: USB on the go full speed
42/121 fields covered. Toggle Registers.
OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
Offset: 0x8, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PTXFELVL
rw |
TXFELVL
rw |
GINT
rw |
|||||||||||||
OTG_FS core interrupt register (OTG_FS_GINTSTS)
Offset: 0x14, reset: 0x04000020, access: Unspecified
11/25 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WKUPINT
rw |
SRQINT
rw |
DISCINT
rw |
CIDSCHG
rw |
PTXFE
r |
HCINT
r |
HPRTINT
r |
IPXFR_INCOMPISOOUT
rw |
IISOIXFR
rw |
OEPINT
r |
IEPINT
r |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EOPF
rw |
ISOODRP
rw |
ENUMDNE
rw |
USBRST
rw |
USBSUSP
rw |
ESUSP
rw |
GOUTNAKEFF
r |
GINAKEFF
r |
NPTXFE
r |
RXFLVL
r |
SOF
rw |
OTGINT
r |
MMIS
rw |
CMOD
r |
||
OTG_FS interrupt mask register (OTG_FS_GINTMSK)
Offset: 0x18, reset: 0x00000000, access: Unspecified
1/25 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WUIM
rw |
SRQIM
rw |
DISCINT
rw |
CIDSCHGM
rw |
PTXFEM
rw |
HCIM
rw |
PRTIM
r |
IPXFRM_IISOOXFRM
rw |
IISOIXFRM
rw |
OEPINT
rw |
IEPINT
rw |
EPMISM
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EOPFM
rw |
ISOODRPM
rw |
ENUMDNEM
rw |
USBRST
rw |
USBSUSPM
rw |
ESUSPM
rw |
GONAKEFFM
rw |
GINAKEFFM
rw |
NPTXFEM
rw |
RXFLVLM
rw |
SOFM
rw |
OTGINT
rw |
MMISM
rw |
|||
OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
Offset: 0x24, reset: 0x00000200, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXFD
rw |
|||||||||||||||
OTG_FS non-periodic transmit FIFO size register (Host mode)
Offset: 0x28, reset: 0x00000200, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NPTXFD
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NPTXFSA
rw |
|||||||||||||||
OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)
Offset: 0x2C, reset: 0x00080200, access: read-only
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NPTXQTOP
r |
NPTQXSAV
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NPTXFSAV
r |
|||||||||||||||
OTG_FS general core configuration register (OTG_FS_GCCFG)
Offset: 0x38, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SOFOUTEN
rw |
VBUSBSEN
rw |
VBUSASEN
rw |
PWRDWN
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
core ID register
Offset: 0x3C, reset: 0x00001000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRODUCT_ID
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRODUCT_ID
rw |
|||||||||||||||
OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
Offset: 0x100, reset: 0x02000600, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PTXFSIZ
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PTXSA
rw |
|||||||||||||||
OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)
Offset: 0x104, reset: 0x02000400, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
INEPTXFD
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INEPTXSA
rw |
|||||||||||||||
0x50000400: USB on the go full speed
10/279 fields covered. Toggle Registers.
OTG_FS host configuration register (OTG_FS_HCFG)
Offset: 0x0, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FSLSS
r |
FSLSPCS
rw |
||||||||||||||
OTG_FS Host frame interval register
Offset: 0x4, reset: 0x0000EA60, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FRIVL
rw |
|||||||||||||||
OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)
Offset: 0x8, reset: 0x00003FFF, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FTREM
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FRNUM
r |
|||||||||||||||
OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
Offset: 0x10, reset: 0x00080100, access: Unspecified
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PTXQTOP
r |
PTXQSAV
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PTXFSAVL
rw |
|||||||||||||||
OTG_FS Host all channels interrupt register
Offset: 0x14, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HAINT
r |
|||||||||||||||
OTG_FS host all channels interrupt mask register
Offset: 0x18, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HAINTM
rw |
|||||||||||||||
OTG_FS host channel-0 transfer size register
Offset: 0x110, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_FS host channel-1 transfer size register
Offset: 0x130, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_FS host channel-2 transfer size register
Offset: 0x150, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_FS host channel-3 transfer size register
Offset: 0x170, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_FS host channel-x transfer size register
Offset: 0x190, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_FS host channel-5 transfer size register
Offset: 0x1B0, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_FS host channel-6 transfer size register
Offset: 0x1D0, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_FS host channel-7 transfer size register
Offset: 0x1F0, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
0x50000E00: USB on the go full speed
0/3 fields covered. Toggle Registers.
OTG_FS power and clock gating control register
Offset: 0x0, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PHYSUSP
rw |
GATEHCLK
rw |
STPPCLK
rw |
|||||||||||||
0x40040800: USB on the go high speed
21/154 fields covered. Toggle Registers.
OTG_HS device all endpoints interrupt register
Offset: 0x18, reset: 0x0, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OEPINT
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IEPINT
r |
|||||||||||||||
OTG_HS all endpoints interrupt mask register
Offset: 0x1C, reset: 0x0, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OEPM
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IEPM
rw |
|||||||||||||||
OTG_HS device VBUS discharge time register
Offset: 0x28, reset: 0x000017D7, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VBUSDT
rw |
|||||||||||||||
OTG_HS device VBUS pulsing time register
Offset: 0x2C, reset: 0x000005B8, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DVBUSP
rw |
|||||||||||||||
OTG_HS Device threshold control register
Offset: 0x30, reset: 0x0, access: read-write
0/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARPEN
rw |
RXTHRLEN
rw |
RXTHREN
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXTHRLEN
rw |
ISOTHREN
rw |
NONISOTHREN
rw |
|||||||||||||
OTG_HS device IN endpoint FIFO empty interrupt mask register
Offset: 0x34, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INEPTXFEM
rw |
|||||||||||||||
OTG_HS device each endpoint interrupt register
Offset: 0x38, reset: 0x0, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OEP1INT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IEP1INT
rw |
|||||||||||||||
OTG_HS device each endpoint interrupt register mask
Offset: 0x3C, reset: 0x0, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OEP1INTM
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IEP1INTM
rw |
|||||||||||||||
OTG device endpoint-0 control register
Offset: 0x100, reset: 0x0, access: Unspecified
2/13 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EPENA
rw |
EPDIS
rw |
SODDFRM
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
TXFNUM
rw |
STALL
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
USBAEP
rw |
MPSIZ
rw |
||||||||||||||
OTG_HS device IN endpoint 0 transfer size register
Offset: 0x110, reset: 0x0, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PKTCNT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS device endpoint-1 DMA address register
Offset: 0x114, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS device IN endpoint transmit FIFO status register
Offset: 0x118, reset: 0x0, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INEPTFSAV
r |
|||||||||||||||
OTG device endpoint-1 control register
Offset: 0x120, reset: 0x0, access: Unspecified
2/13 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EPENA
rw |
EPDIS
rw |
SODDFRM
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
TXFNUM
rw |
STALL
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
USBAEP
rw |
MPSIZ
rw |
||||||||||||||
OTG_HS device endpoint transfer size register
Offset: 0x130, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS device endpoint-2 DMA address register
Offset: 0x134, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS device endpoint-3 DMA address register
Offset: 0x154, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS device endpoint-4 DMA address register
Offset: 0x174, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS device endpoint-5 DMA address register
Offset: 0x194, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS device endpoint-1 transfer size register
Offset: 0x310, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
STUPCNT
rw |
PKTCNT
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG device endpoint-1 control register
Offset: 0x320, reset: 0x0, access: Unspecified
2/13 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EPENA
rw |
EPDIS
rw |
SODDFRM
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
STALL
rw |
SNPM
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
USBAEP
rw |
MPSIZ
rw |
||||||||||||||
OTG_HS device endpoint-2 transfer size register
Offset: 0x330, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RXDPID_STUPCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
0x40040000: USB on the go high speed
41/136 fields covered. Toggle Registers.
OTG_HS core interrupt register
Offset: 0x14, reset: 0x04000020, access: Unspecified
11/26 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WKUPINT
rw |
SRQINT
rw |
DISCINT
rw |
CIDSCHG
rw |
PTXFE
r |
HCINT
r |
HPRTINT
r |
DATAFSUSP
rw |
PXFR_INCOMPISOOUT
rw |
IISOIXFR
rw |
OEPINT
r |
IEPINT
r |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EOPF
rw |
ISOODRP
rw |
ENUMDNE
rw |
USBRST
rw |
USBSUSP
rw |
ESUSP
rw |
BOUTNAKEFF
r |
GINAKEFF
r |
NPTXFE
r |
RXFLVL
r |
SOF
rw |
OTGINT
r |
MMIS
rw |
CMOD
r |
||
OTG_HS interrupt mask register
Offset: 0x18, reset: 0x0, access: Unspecified
1/26 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WUIM
rw |
SRQIM
rw |
DISCINT
rw |
CIDSCHGM
rw |
PTXFEM
rw |
HCIM
rw |
PRTIM
r |
FSUSPM
rw |
PXFRM_IISOOXFRM
rw |
IISOIXFRM
rw |
OEPINT
rw |
IEPINT
rw |
EPMISM
rw |
|||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EOPFM
rw |
ISOODRPM
rw |
ENUMDNEM
rw |
USBRST
rw |
USBSUSPM
rw |
ESUSPM
rw |
GONAKEFFM
rw |
GINAKEFFM
rw |
NPTXFEM
rw |
RXFLVLM
rw |
SOFM
rw |
OTGINT
rw |
MMISM
rw |
|||
OTG_HS Receive FIFO size register
Offset: 0x24, reset: 0x00000200, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXFD
rw |
|||||||||||||||
Endpoint 0 transmit FIFO size (peripheral mode)
Offset: 0x28, reset: 0x00000200, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TX0FD
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TX0FSA
rw |
|||||||||||||||
OTG_HS nonperiodic transmit FIFO/queue status register
Offset: 0x2C, reset: 0x00080200, access: read-only
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NPTXQTOP
r |
NPTQXSAV
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NPTXFSAV
r |
|||||||||||||||
OTG_HS general core configuration register
Offset: 0x38, reset: 0x0, access: read-write
0/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NOVBUSSENS
rw |
SOFOUTEN
rw |
VBUSBSEN
rw |
VBUSASEN
rw |
I2CPADEN
rw |
PWRDWN
rw |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OTG_HS core ID register
Offset: 0x3C, reset: 0x00001200, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRODUCT_ID
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRODUCT_ID
rw |
|||||||||||||||
OTG_HS Host periodic transmit FIFO size register
Offset: 0x100, reset: 0x02000600, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PTXFD
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PTXSA
rw |
|||||||||||||||
OTG_HS device IN endpoint transmit FIFO size register
Offset: 0x104, reset: 0x02000400, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
INEPTXFD
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INEPTXSA
rw |
|||||||||||||||
0x40040400: USB on the go high speed
10/515 fields covered. Toggle Registers.
OTG_HS host configuration register
Offset: 0x0, reset: 0x0, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FSLSS
r |
FSLSPCS
rw |
||||||||||||||
OTG_HS Host frame interval register
Offset: 0x4, reset: 0x0000EA60, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FRIVL
rw |
|||||||||||||||
OTG_HS host frame number/frame time remaining register
Offset: 0x8, reset: 0x00003FFF, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FTREM
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FRNUM
r |
|||||||||||||||
OTG_HS_Host periodic transmit FIFO/queue status register
Offset: 0x10, reset: 0x00080100, access: Unspecified
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PTXQTOP
r |
PTXQSAV
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PTXFSAVL
rw |
|||||||||||||||
OTG_HS Host all channels interrupt register
Offset: 0x14, reset: 0x0, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HAINT
r |
|||||||||||||||
OTG_HS host all channels interrupt mask register
Offset: 0x18, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HAINTM
rw |
|||||||||||||||
OTG_HS host channel-11 transfer size register
Offset: 0x110, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS host channel-0 DMA address register
Offset: 0x114, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS host channel-1 transfer size register
Offset: 0x130, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS host channel-1 DMA address register
Offset: 0x134, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS host channel-2 transfer size register
Offset: 0x150, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS host channel-2 DMA address register
Offset: 0x154, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS host channel-3 transfer size register
Offset: 0x170, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS host channel-3 DMA address register
Offset: 0x174, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS host channel-4 transfer size register
Offset: 0x190, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS host channel-4 DMA address register
Offset: 0x194, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS host channel-5 transfer size register
Offset: 0x1B0, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS host channel-5 DMA address register
Offset: 0x1B4, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS host channel-6 transfer size register
Offset: 0x1D0, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS host channel-6 DMA address register
Offset: 0x1D4, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS host channel-7 transfer size register
Offset: 0x1F0, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS host channel-7 DMA address register
Offset: 0x1F4, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS host channel-8 transfer size register
Offset: 0x210, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS host channel-8 DMA address register
Offset: 0x214, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS host channel-9 transfer size register
Offset: 0x230, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS host channel-9 DMA address register
Offset: 0x234, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS host channel-10 transfer size register
Offset: 0x250, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS host channel-10 DMA address register
Offset: 0x254, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
OTG_HS host channel-11 transfer size register
Offset: 0x270, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DPID
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
XFRSIZ
rw |
|||||||||||||||
OTG_HS host channel-11 DMA address register
Offset: 0x274, reset: 0x0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAADDR
rw |
|||||||||||||||
0x40040E00: USB on the go high speed
0/3 fields covered. Toggle Registers.
Power and clock gating control register
Offset: 0x0, reset: 0x0, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PHYSUSP
rw |
GATEHCLK
rw |
STPPCLK
rw |
|||||||||||||
0x40007000: Power control
4/15 fields covered. Toggle Registers.
0x40023800: Reset and clock control
243/243 fields covered. Toggle Registers.
clock configuration register
Offset: 0x8, reset: 0x00000000, access: Unspecified
11/11 fields covered.
Bits 4-7: AHB prescaler.
Allowed values:
0: Div1: SYSCLK not divided
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
clock interrupt register
Offset: 0xC, reset: 0x00000000, access: Unspecified
20/20 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CSSC
w |
PLLI2SRDYC
w |
PLLRDYC
w |
HSERDYC
w |
HSIRDYC
w |
LSERDYC
w |
LSIRDYC
w |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PLLI2SRDYIE
rw |
PLLRDYIE
rw |
HSERDYIE
rw |
HSIRDYIE
rw |
LSERDYIE
rw |
LSIRDYIE
rw |
CSSF
r |
PLLI2SRDYF
r |
PLLRDYF
r |
HSERDYF
r |
HSIRDYF
r |
LSERDYF
r |
LSIRDYF
r |
|||
AHB2 peripheral reset register
Offset: 0x14, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OTGFSRST
rw |
RNGRST
rw |
DCMIRST
rw |
|||||||||||||
AHB3 peripheral reset register
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FSMCRST
rw |
|||||||||||||||
APB1 peripheral reset register
Offset: 0x20, reset: 0x00000000, access: read-write
23/23 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACRST
rw |
PWRRST
rw |
CAN2RST
rw |
CAN1RST
rw |
I2C3RST
rw |
I2C2RST
rw |
I2C1RST
rw |
UART5RST
rw |
UART4RST
rw |
UART3RST
rw |
UART2RST
rw |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SPI3RST
rw |
SPI2RST
rw |
WWDGRST
rw |
TIM14RST
rw |
TIM13RST
rw |
TIM12RST
rw |
TIM7RST
rw |
TIM6RST
rw |
TIM5RST
rw |
TIM4RST
rw |
TIM3RST
rw |
TIM2RST
rw |
||||
AHB1 peripheral clock register
Offset: 0x30, reset: 0x00100000, access: read-write
19/19 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OTGHSULPIEN
rw |
OTGHSEN
rw |
ETHMACPTPEN
rw |
ETHMACRXEN
rw |
ETHMACTXEN
rw |
ETHMACEN
rw |
DMA2EN
rw |
DMA1EN
rw |
BKPSRAMEN
rw |
|||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCEN
rw |
GPIOIEN
rw |
GPIOHEN
rw |
GPIOGEN
rw |
GPIOFEN
rw |
GPIOEEN
rw |
GPIODEN
rw |
GPIOCEN
rw |
GPIOBEN
rw |
GPIOAEN
rw |
||||||
AHB2 peripheral clock enable register
Offset: 0x34, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OTGFSEN
rw |
RNGEN
rw |
DCMIEN
rw |
|||||||||||||
AHB3 peripheral clock enable register
Offset: 0x38, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FSMCEN
rw |
|||||||||||||||
APB1 peripheral clock enable register
Offset: 0x40, reset: 0x00000000, access: read-write
23/23 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACEN
rw |
PWREN
rw |
CAN2EN
rw |
CAN1EN
rw |
I2C3EN
rw |
I2C2EN
rw |
I2C1EN
rw |
UART5EN
rw |
UART4EN
rw |
USART3EN
rw |
USART2EN
rw |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SPI3EN
rw |
SPI2EN
rw |
WWDGEN
rw |
TIM14EN
rw |
TIM13EN
rw |
TIM12EN
rw |
TIM7EN
rw |
TIM6EN
rw |
TIM5EN
rw |
TIM4EN
rw |
TIM3EN
rw |
TIM2EN
rw |
||||
AHB1 peripheral clock enable in low power mode register
Offset: 0x50, reset: 0x7E6791FF, access: read-write
22/22 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OTGHSULPILPEN
rw |
OTGHSLPEN
rw |
ETHMACPTPLPEN
rw |
ETHMACRXLPEN
rw |
ETHMACTXLPEN
rw |
ETHMACLPEN
rw |
DMA2LPEN
rw |
DMA1LPEN
rw |
BKPSRAMLPEN
rw |
SRAM2LPEN
rw |
SRAM1LPEN
rw |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FLITFLPEN
rw |
CRCLPEN
rw |
GPIOILPEN
rw |
GPIOHLPEN
rw |
GPIOGLPEN
rw |
GPIOFLPEN
rw |
GPIOELPEN
rw |
GPIODLPEN
rw |
GPIOCLPEN
rw |
GPIOBLPEN
rw |
GPIOALPEN
rw |
|||||
AHB2 peripheral clock enable in low power mode register
Offset: 0x54, reset: 0x000000F1, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OTGFSLPEN
rw |
RNGLPEN
rw |
DCMILPEN
rw |
|||||||||||||
AHB3 peripheral clock enable in low power mode register
Offset: 0x58, reset: 0x00000001, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FSMCLPEN
rw |
|||||||||||||||
APB1 peripheral clock enable in low power mode register
Offset: 0x60, reset: 0x36FEC9FF, access: read-write
23/23 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACLPEN
rw |
PWRLPEN
rw |
CAN2LPEN
rw |
CAN1LPEN
rw |
I2C3LPEN
rw |
I2C2LPEN
rw |
I2C1LPEN
rw |
UART5LPEN
rw |
UART4LPEN
rw |
USART3LPEN
rw |
USART2LPEN
rw |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SPI3LPEN
rw |
SPI2LPEN
rw |
WWDGLPEN
rw |
TIM14LPEN
rw |
TIM13LPEN
rw |
TIM12LPEN
rw |
TIM7LPEN
rw |
TIM6LPEN
rw |
TIM5LPEN
rw |
TIM4LPEN
rw |
TIM3LPEN
rw |
TIM2LPEN
rw |
||||
APB2 peripheral clock enabled in low power mode register
Offset: 0x64, reset: 0x00075F33, access: read-write
13/13 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TIM11LPEN
rw |
TIM10LPEN
rw |
TIM9LPEN
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SYSCFGLPEN
rw |
SPI1LPEN
rw |
SDIOLPEN
rw |
ADC3LPEN
rw |
ADC2LPEN
rw |
ADC1LPEN
rw |
USART6LPEN
rw |
USART1LPEN
rw |
TIM8LPEN
rw |
TIM1LPEN
rw |
||||||
PLLI2S configuration register
Offset: 0x84, reset: 0x20003000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PLLI2SR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PLLI2SN
rw |
|||||||||||||||
0x50060800: Random number generator
6/8 fields covered. Toggle Registers.
control register
Offset: 0x0, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IE
rw |
RNGEN
rw |
||||||||||||||
data register
Offset: 0x8, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RNDATA
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RNDATA
r |
|||||||||||||||
0x40002800: Real-time clock
106/122 fields covered. Toggle Registers.
control register
Offset: 0x8, reset: 0x00000000, access: read-write
20/21 fields covered.
Bits 0-2: Wakeup clock selection.
Allowed values:
0: Div16: RTC/16 clock is selected
1: Div8: RTC/8 clock is selected
2: Div4: RTC/4 clock is selected
3: Div2: RTC/2 clock is selected
4: ClockSpare: ck_spre (usually 1 Hz) clock is selected
6: ClockSpareWithOffset: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
Bit 5: Bypass the shadow registers.
Allowed values:
0: ShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
1: BypassShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
prescaler register
Offset: 0x10, reset: 0x007F00FF, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PREDIV_A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PREDIV_S
rw |
|||||||||||||||
wakeup timer register
Offset: 0x14, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WUT
rw |
|||||||||||||||
calibration register
Offset: 0x18, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DCS
rw |
DC
rw |
||||||||||||||
write protection register
Offset: 0x24, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
KEY
w |
|||||||||||||||
sub second register
Offset: 0x28, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
r |
|||||||||||||||
shift control register
Offset: 0x2C, reset: 0x00000000, access: write-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADD1S
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SUBFS
w |
|||||||||||||||
time stamp time register
Offset: 0x30, reset: 0x00000000, access: read-only
6/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ALARMOUTTYPE
r |
TSINSEL
r |
TAMP1INSEL
r |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TAMPIE
r |
TAMP1TRG
r |
TAMP1E
r |
|||||||||||||
timestamp sub second register
Offset: 0x38, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
r |
|||||||||||||||
calibration register
Offset: 0x3C, reset: 0x00000000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CALP
rw |
CALW8
rw |
CALW16
rw |
CALM
rw |
||||||||||||
tamper and alternate function configuration register
Offset: 0x40, reset: 0x00000000, access: read-write
0/13 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ALARMOUTTYPE
rw |
TSINSEL
rw |
TAMP1INSEL
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TAMPPUDIS
rw |
TAMPPRCH
rw |
TAMPFLT
rw |
TAMPFREQ
rw |
TAMPTS
rw |
TAMP2TRG
rw |
TAMP2E
rw |
TAMPIE
rw |
TAMP1TRG
rw |
TAMP1E
rw |
||||||
alarm A sub second register
Offset: 0x44, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MASKSS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
rw |
|||||||||||||||
alarm B sub second register
Offset: 0x48, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MASKSS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
rw |
|||||||||||||||
backup register
Offset: 0x50, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
0x40015800: Serial audio interface
43/51 fields covered. Toggle Registers.
SAI AConfiguration register 1
Offset: 0x0, reset: 0x00000040, access: read-write
11/12 fields covered.
Bits 10-11: Synchronization enable.
Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
SAI ASlot register
Offset: 0xC, reset: 0x00000000, access: read-write
2/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SLOTEN
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NBSLOT
rw |
SLOTSZ
rw |
FBOFF
rw |
|||||||||||||
SAI AData register
Offset: 0x1C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DATA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATA
rw |
|||||||||||||||
0xE000ED00: System control block
5/74 fields covered. Toggle Registers.
CPUID base register
Offset: 0x0, reset: 0x410FC241, access: read-only
5/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Implementer
r |
Variant
r |
Constant
r |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PartNo
r |
Revision
r |
||||||||||||||
Interrupt control and state register
Offset: 0x4, reset: 0x00000000, access: read-write
0/9 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NMIPENDSET
rw |
PENDSVSET
rw |
PENDSVCLR
rw |
PENDSTSET
rw |
PENDSTCLR
rw |
ISRPENDING
rw |
VECTPENDING
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VECTPENDING
rw |
RETTOBASE
rw |
VECTACTIVE
rw |
|||||||||||||
Vector table offset register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TBLOFF
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TBLOFF
rw |
|||||||||||||||
Application interrupt and reset control register
Offset: 0xC, reset: 0x00000000, access: read-write
0/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
VECTKEYSTAT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ENDIANESS
rw |
PRIGROUP
rw |
SYSRESETREQ
rw |
VECTCLRACTIVE
rw |
VECTRESET
rw |
|||||||||||
System control register
Offset: 0x10, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SEVEONPEND
rw |
SLEEPDEEP
rw |
SLEEPONEXIT
rw |
|||||||||||||
Configuration and control register
Offset: 0x14, reset: 0x00000000, access: read-write
0/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STKALIGN
rw |
BFHFNMIGN
rw |
DIV_0_TRP
rw |
UNALIGN__TRP
rw |
USERSETMPEND
rw |
NONBASETHRDENA
rw |
||||||||||
System handler priority registers
Offset: 0x18, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRI_6
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRI_5
rw |
PRI_4
rw |
||||||||||||||
System handler priority registers
Offset: 0x1C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRI_11
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
System handler priority registers
Offset: 0x20, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRI_15
rw |
PRI_14
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
System handler control and state register
Offset: 0x24, reset: 0x00000000, access: read-write
0/14 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
USGFAULTENA
rw |
BUSFAULTENA
rw |
MEMFAULTENA
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SVCALLPENDED
rw |
BUSFAULTPENDED
rw |
MEMFAULTPENDED
rw |
USGFAULTPENDED
rw |
SYSTICKACT
rw |
PENDSVACT
rw |
MONITORACT
rw |
SVCALLACT
rw |
USGFAULTACT
rw |
BUSFAULTACT
rw |
MEMFAULTACT
rw |
|||||
Configurable fault status register
Offset: 0x28, reset: 0x00000000, access: read-write
0/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DIVBYZERO
rw |
UNALIGNED
rw |
NOCP
rw |
INVPC
rw |
INVSTATE
rw |
UNDEFINSTR
rw |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BFARVALID
rw |
LSPERR
rw |
STKERR
rw |
UNSTKERR
rw |
IMPRECISERR
rw |
PRECISERR
rw |
IBUSERR
rw |
MMARVALID
rw |
MLSPERR
rw |
MSTKERR
rw |
MUNSTKERR
rw |
IACCVIOL
rw |
||||
Hard fault status register
Offset: 0x2C, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DEBUG_VT
rw |
FORCED
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VECTTBL
rw |
|||||||||||||||
Memory management fault address register
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MMFAR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMFAR
rw |
|||||||||||||||
Bus fault address register
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BFAR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BFAR
rw |
|||||||||||||||
Auxiliary fault status register
Offset: 0x3C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IMPDEF
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IMPDEF
rw |
|||||||||||||||
0xE000E008: System control block ACTLR
0/5 fields covered. Toggle Registers.
Auxiliary control register
Offset: 0x0, reset: 0x00000000, access: read-write
0/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DISOOFP
rw |
DISFPCA
rw |
DISFOLD
rw |
DISDEFWBUF
rw |
DISMCYCINT
rw |
|||||||||||
0x40012C00: Secure digital input/output interface
98/98 fields covered. Toggle Registers.
power control register
Offset: 0x0, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PWRCTRL
rw |
|||||||||||||||
argument register
Offset: 0x8, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CMDARG
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMDARG
rw |
|||||||||||||||
command register
Offset: 0xC, reset: 0x00000000, access: read-write
9/9 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CE_ATACMD
rw |
nIEN
rw |
ENCMDcompl
rw |
SDIOSuspend
rw |
CPSMEN
rw |
WAITPEND
rw |
WAITINT
rw |
WAITRESP
rw |
CMDINDEX
rw |
|||||||
command response register
Offset: 0x10, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RESPCMD
r |
|||||||||||||||
response 1..4 register
Offset: 0x14, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CARDSTATUS1
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CARDSTATUS1
r |
|||||||||||||||
response 1..4 register
Offset: 0x18, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CARDSTATUS2
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CARDSTATUS2
r |
|||||||||||||||
response 1..4 register
Offset: 0x1C, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CARDSTATUS3
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CARDSTATUS3
r |
|||||||||||||||
response 1..4 register
Offset: 0x20, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CARDSTATUS4
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CARDSTATUS4
r |
|||||||||||||||
data timer register
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DATATIME
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATATIME
rw |
|||||||||||||||
data length register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DATALENGTH
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATALENGTH
rw |
|||||||||||||||
data control register
Offset: 0x2C, reset: 0x00000000, access: read-write
9/9 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SDIOEN
rw |
RWMOD
rw |
RWSTOP
rw |
RWSTART
rw |
DBLOCKSIZE
rw |
DMAEN
rw |
DTMODE
rw |
DTDIR
rw |
DTEN
rw |
|||||||
data counter register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DATACOUNT
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATACOUNT
r |
|||||||||||||||
status register
Offset: 0x34, reset: 0x00000000, access: read-only
24/24 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CEATAEND
r |
SDIOIT
r |
RXDAVL
r |
TXDAVL
r |
RXFIFOE
r |
TXFIFOE
r |
RXFIFOF
r |
TXFIFOF
r |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXFIFOHF
r |
TXFIFOHE
r |
RXACT
r |
TXACT
r |
CMDACT
r |
DBCKEND
r |
STBITERR
r |
DATAEND
r |
CMDSENT
r |
CMDREND
r |
RXOVERR
r |
TXUNDERR
r |
DTIMEOUT
r |
CTIMEOUT
r |
DCRCFAIL
r |
CCRCFAIL
r |
mask register
Offset: 0x3C, reset: 0x00000000, access: read-write
24/24 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CEATAENDIE
rw |
SDIOITIE
rw |
RXDAVLIE
rw |
TXDAVLIE
rw |
RXFIFOEIE
rw |
TXFIFOEIE
rw |
RXFIFOFIE
rw |
TXFIFOFIE
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXFIFOHFIE
rw |
TXFIFOHEIE
rw |
RXACTIE
rw |
TXACTIE
rw |
CMDACTIE
rw |
DBCKENDIE
rw |
STBITERRIE
rw |
DATAENDIE
rw |
CMDSENTIE
rw |
CMDRENDIE
rw |
RXOVERRIE
rw |
TXUNDERRIE
rw |
DTIMEOUTIE
rw |
CTIMEOUTIE
rw |
DCRCFAILIE
rw |
CCRCFAILIE
rw |
FIFO counter register
Offset: 0x48, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FIFOCOUNT
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FIFOCOUNT
r |
|||||||||||||||
data FIFO register
Offset: 0x80, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FIFOData
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FIFOData
rw |
|||||||||||||||
0x40013000: Serial peripheral interface
45/45 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40003800: Serial peripheral interface
45/45 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40003C00: Serial peripheral interface
45/45 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40013400: Serial peripheral interface
45/45 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40015000: Serial peripheral interface
45/45 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40015400: Serial peripheral interface
45/45 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0xE000E010: SysTick timer
0/9 fields covered. Toggle Registers.
SysTick control and status register
Offset: 0x0, reset: 0X00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
COUNTFLAG
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLKSOURCE
rw |
TICKINT
rw |
ENABLE
rw |
|||||||||||||
SysTick reload value register
Offset: 0x4, reset: 0X00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RELOAD
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RELOAD
rw |
|||||||||||||||
SysTick current value register
Offset: 0x8, reset: 0X00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CURRENT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CURRENT
rw |
|||||||||||||||
SysTick calibration value register
Offset: 0xC, reset: 0X00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NOREF
rw |
SKEW
rw |
TENMS
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TENMS
rw |
|||||||||||||||
0x40013800: System configuration controller
2/20 fields covered. Toggle Registers.
memory remap register
Offset: 0x0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MEM_MODE
rw |
|||||||||||||||
peripheral mode configuration register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MII_RMII_SEL
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
external interrupt configuration register 1
Offset: 0x8, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI3
rw |
EXTI2
rw |
EXTI1
rw |
EXTI0
rw |
||||||||||||
external interrupt configuration register 2
Offset: 0xC, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI7
rw |
EXTI6
rw |
EXTI5
rw |
EXTI4
rw |
||||||||||||
external interrupt configuration register 3
Offset: 0x10, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI11
rw |
EXTI10
rw |
EXTI9
rw |
EXTI8
rw |
||||||||||||
external interrupt configuration register 4
Offset: 0x14, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI15
rw |
EXTI14
rw |
EXTI13
rw |
EXTI12
rw |
||||||||||||
Compensation cell control register
Offset: 0x20, reset: 0x00000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
READY
r |
CMP_PD
r |
||||||||||||||
0x40010000: Advanced-timers
77/124 fields covered. Toggle Registers.
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
8/8 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/12 fields covered.
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REP
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4C, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
0x40014400: General-purpose-timers
10/27 fields covered. Toggle Registers.
DMA/Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1IE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
1/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1OF
rw |
CC1IF
rw |
UIF
rw |
|||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1G
w |
UG
w |
||||||||||||||
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IC1F
rw |
IC1PSC
rw |
CC1S
rw |
|||||||||||||
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1NP
rw |
CC1P
rw |
CC1E
rw |
|||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
0x40014800: General-purpose-timers
10/28 fields covered. Toggle Registers.
DMA/Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1IE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
1/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1OF
rw |
CC1IF
rw |
UIF
rw |
|||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1G
w |
UG
w |
||||||||||||||
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IC1F
rw |
IC1PSC
rw |
CC1S
rw |
|||||||||||||
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1NP
rw |
CC1P
rw |
CC1E
rw |
|||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
option register
Offset: 0x50, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RMP
rw |
|||||||||||||||
0x40001800: General purpose timers
10/48 fields covered. Toggle Registers.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMS
rw |
|||||||||||||||
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MSM
rw |
TS
rw |
SMS
rw |
|||||||||||||
DMA/Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
1/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIE
rw |
CC2IE
rw |
CC1IE
rw |
UIE
rw |
||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TG
w |
CC2G
w |
CC1G
w |
UG
w |
||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
0x40001C00: General-purpose-timers
10/27 fields covered. Toggle Registers.
DMA/Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1IE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
1/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1OF
rw |
CC1IF
rw |
UIF
rw |
|||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1G
w |
UG
w |
||||||||||||||
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IC1F
rw |
IC1PSC
rw |
CC1S
rw |
|||||||||||||
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1NP
rw |
CC1P
rw |
CC1E
rw |
|||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
0x40002000: General-purpose-timers
10/27 fields covered. Toggle Registers.
DMA/Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1IE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
1/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1OF
rw |
CC1IF
rw |
UIF
rw |
|||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1G
w |
UG
w |
||||||||||||||
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IC1F
rw |
IC1PSC
rw |
CC1S
rw |
|||||||||||||
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1NP
rw |
CC1P
rw |
CC1E
rw |
|||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
0x40000000: General purpose timers
74/98 fields covered. Toggle Registers.
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
8/8 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1S
rw |
MMS
rw |
CCDS
rw |
|||||||||||||
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4C, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
TIM5 option register
Offset: 0x50, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ITR1_RMP
rw |
|||||||||||||||
0x40000400: General purpose timers
74/100 fields covered. Toggle Registers.
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
8/8 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1S
rw |
MMS
rw |
CCDS
rw |
|||||||||||||
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT_H
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR_H
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR1_H
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4C, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
0x40000800: General purpose timers
74/100 fields covered. Toggle Registers.
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
8/8 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1S
rw |
MMS
rw |
CCDS
rw |
|||||||||||||
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT_H
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR_H
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR1_H
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4C, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
0x40000C00: General-purpose-timers
74/98 fields covered. Toggle Registers.
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
8/8 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1S
rw |
MMS
rw |
CCDS
rw |
|||||||||||||
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4C, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
TIM5 option register
Offset: 0x50, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IT4_RMP
rw |
|||||||||||||||
0x40001000: Basic timers
13/13 fields covered. Toggle Registers.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMS
rw |
|||||||||||||||
DMA/Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UDE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UIF
rw |
|||||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UG
w |
|||||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
0x40001400: Basic timers
13/13 fields covered. Toggle Registers.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMS
rw |
|||||||||||||||
DMA/Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UDE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UIF
rw |
|||||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UG
w |
|||||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
0x40010400: Advanced-timers
77/124 fields covered. Toggle Registers.
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
8/8 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/12 fields covered.
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REP
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4C, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
0x40014000: General purpose timers
10/48 fields covered. Toggle Registers.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMS
rw |
|||||||||||||||
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MSM
rw |
TS
rw |
SMS
rw |
|||||||||||||
DMA/Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
1/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIE
rw |
CC2IE
rw |
CC1IE
rw |
UIE
rw |
||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TG
w |
CC2G
w |
CC1G
w |
UG
w |
||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2C, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
0x40004C00: Universal synchronous asynchronous receiver transmitter
36/39 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Baud rate register
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIV_Mantissa
rw |
DIV_Fraction
rw |
||||||||||||||
0x40005000: Universal synchronous asynchronous receiver transmitter
36/39 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Baud rate register
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIV_Mantissa
rw |
DIV_Fraction
rw |
||||||||||||||
0x40007800: Universal synchronous asynchronous receiver transmitter
36/39 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Baud rate register
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIV_Mantissa
rw |
DIV_Fraction
rw |
||||||||||||||
0x40007C00: Universal synchronous asynchronous receiver transmitter
36/39 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Baud rate register
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIV_Mantissa
rw |
DIV_Fraction
rw |
||||||||||||||
0x40011000: Universal synchronous asynchronous receiver transmitter
44/51 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Baud rate register
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIV_Mantissa
rw |
DIV_Fraction
rw |
||||||||||||||
Guard time and prescaler register
Offset: 0x18, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
0x40004400: Universal synchronous asynchronous receiver transmitter
44/51 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Baud rate register
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIV_Mantissa
rw |
DIV_Fraction
rw |
||||||||||||||
Guard time and prescaler register
Offset: 0x18, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
0x40004800: Universal synchronous asynchronous receiver transmitter
44/51 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Baud rate register
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIV_Mantissa
rw |
DIV_Fraction
rw |
||||||||||||||
Guard time and prescaler register
Offset: 0x18, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
0x40011400: Universal synchronous asynchronous receiver transmitter
44/51 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Baud rate register
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIV_Mantissa
rw |
DIV_Fraction
rw |
||||||||||||||
Guard time and prescaler register
Offset: 0x18, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
0x40002C00: Window watchdog
6/6 fields covered. Toggle Registers.
Control register
Offset: 0x0, reset: 0x7F, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WDGA
rw |
T
rw |
||||||||||||||
Configuration register
Offset: 0x4, reset: 0x7F, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EWI
rw |
WDGTB
rw |
W
rw |
|||||||||||||
Status register
Offset: 0x8, reset: 0x00, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EWIF
rw |
|||||||||||||||